The disclosed concepts relate to a semiconductor memory device, and more particularly, to a semiconductor memory device including a support structure pattern to prevent a collapse of lower electrodes.
Recently, as an integration of memory devices has been accelerated due to the rapid development of micronized semiconductor process technology, the size of a unit cell has been significantly reduced and an operating voltage has been noticeably lowered. For example, the level of integration of semiconductor memory devices, such as dynamic random access memory (DRAM), has increased and areas occupied by devices have decreased, while capacitance has been required to be maintained or increased.
Some example embodiments provide a semiconductor memory device having enhanced reliability by improving operation defects of information storage components and simultaneously enhancing the level of integration.